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NB100LVEP221 2.5V/3.3V 1:20 Differential HSTL/ECL/PECL Clock Driver
The NB100LVEP221 is a low skew 1-to-20 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential ECL/PECL; CLK1/CLK1 can also receive HSTL signal levels. The LVPECL input signals can be either differential configuration or single-ended (if the VBB output is used). The LVEP221 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure tightest skew, both sides of differential outputs should be terminated identically into 50 W even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. The NB100LVEP221, as with most other ECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the LVEP221 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on PECL terminations, designers should refer to Application Note AND8020/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single- ended LVPECL input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Single- ended CLK input operation is limited to a VCC 3.0 V in LVPECL mode, or VEE -3.0 V in NECL mode.
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NB100 LVEP221 AWLYYWW 52-LEAD LQFP THERMALLY ENHANCED CASE 848H FA SUFFIX A WL YY WW
52 1
= Assembly Location = Wafer Lot = Year = Work Week
*For additional information, refer to Application Note AND8002/D
ORDERING INFORMATION
Device NB100LVEP221FA NB100LVEP221FAR2 Package LQFP-52 Shipping 160 Units/Tray
* * * * * * * * * * *
15 ps Typical Output-to-Output Skew 40 ps Typical Device-to- Device Skew Jitter Less than 2 ps RMS Maximum Frequency > 1.0 GHz Typical Thermally Enhanced 52-Lead LQFP VBB Output 540 ps Typical Propagation Delay LVPECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V Q Output will Default Low with Inputs Open or at VEE Pin Compatible with Motorola MC100EP221
LQFP-52 1500/Tape & Reel
(c) Semiconductor Components Industries, LLC, 2003
1
January, 2003 - Rev. 4
Publication Order Number: NB100LVEP221/D
NB100LVEP221
VCC0 27 26 25 24 23 22 21 Q12 Q12 Q13 Q13 Q14 Q14 Q15 Q15 Q16 Q16 Q17 Q17 VCC0 20 19 18 17 16 15 14 1 2 3 4 5 6 7 8 9 10 11 12 13 0 CLK0 CLK1 1 CLK1 VBB CLK_SEL VCC VEE 20 Q0 - Q19 Q0 - Q19 20 Q18 Q10 Q10 Q11 29 Q19 Q11 28 Q18 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9
39 VCC0 Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 40 41 42 43 44 45 46 47 48 49 50 51 52
38
37
36
35
34
33
32
31
30
NB100LVEP221
CLKSEL
CLK0
CLK1
CLK0
CLK1
VCC0
VCC
All VCC, VCCO, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a heat-sinking conduit, capable of transferring 1.2 Watts. This exposed pad is electrically connected to VEE internally.
Figure 1. 52-Lead LQFP Pinout (Top View) PIN DESCRIPTION
PIN CLK0*, CLK0** CLK1*, CLK1** Q0:19, Q0:19 CLK_SEL* VBB VCC/VCCO VEE*** FUNCTION ECL/PECL Differential Inputs ECL/PECL or HSTL Differential Inputs ECL/PECL Differential Outputs ECL/PECL Active Clock Select Input Reference Voltage Output Positive Supply Negative Supply CLK0
* Pins will default LOW when left open. ** Pins will default HIGH when left open. *** The thermally conductive exposed pad on the bottom of the package is electrically connected to VEE internally.
FUNCTION TABLE
CLK_SEL L H Active Input CLK0, CLK0 CLK1, CLK1
Figure 2. Logic Diagram
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Q19
VBB
VEE
NB100LVEP221
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Oxygen Index: 28 to 34 Value 75 kW 37.5 kW > 2 kV > 200 V > 2 kV Level 3 UL 94 V-0 @ 0.125 in 533 Devices
Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (See Application Information) Thermal Resistance (Junction-to-Case) (See Application Information) Wave Solder 0 LFPM 500 LFPM 0 LFPM 500 LFPM < 2 to 3 sec @ 248C 52 LQFP 52 LQFP 52 LQFP 52 LQFP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 35.6 30 3.2 6.4 265 Units V V V V mA mA mA C C C/W C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
LVPECL DC CHARACTERISTICS VCC = 2.5 V; VEE = 0 V (Note 3)
-40 C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) (Note 5) Input LOW Voltage (Single-Ended) (Note 5) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) CLK0/CLK0 CLK1/CLK1 Input HIGH Current Input LOW Current CLK CLK 0.5 -150 Min 100 1355 555 1335 555 Typ 125 1480 680 Max 150 1605 900 1620 900 Min 104 1355 555 1335 555 25C Typ 130 1480 680 Max 156 1605 900 1620 900 Min 116 1355 555 1275 555 85C Typ 145 1480 680 Max 174 1605 900 1620 900 Unit mA mV mV mV mV
1.2 0.3
2.5 1.6 150
1.2 0.3
2.5 1.6 150
1.2 0.3
2.5 1.6 150
V V mA mA
IIH IIL NOTE: 3. 4. 5. 6.
0.5 -150
0.5 -150
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.125 V to -1.3 V. All outputs loaded with 50 W to VCC - 2.0 V. Do not use VBB at VCC < 3.0 V. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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NB100LVEP221
LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V (Note 7)
-40 C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 8) Output LOW Voltage (Note 8) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Reference Voltage (Note 9) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) CLK0/CLK0 CLK1/CLK1 Input HIGH Current Input LOW Current CLK CLK 0.5 -150 Min 100 2155 1355 2135 1355 1775 1875 Typ 125 2280 1480 Max 150 2405 1700 2420 1700 1975 Min 104 2155 1355 2135 1355 1775 1875 25C Typ 130 2280 1480 Max 156 2405 1700 2420 1700 1975 Min 116 2155 1355 2135 1355 1775 1875 85C Typ 145 2280 1480 Max 174 2405 1700 2420 1700 1975 Unit mA mV mV mV mV mV
1.2 0.3
3.3 1.6 150
1.2 0.3
3.3 1.6 150
1.2 0.3
3.3 1.6 150
V V mA mA
IIH IIL NOTE:
0.5 -150
0.5 -150
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 7. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.925 V to -0.5 V. 8. All outputs loaded with 50 W to VCC - 2.0 V. 9. Single-ended input operation is limited VCC 3.0 V in LVPECL mode. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
LVNECL DC CHARACTERISTICS VCC = 0 V, VEE = -2.375 V to -3.8 V (Note 11)
-40 C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 12) Output LOW Voltage (Note 12) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Reference Voltage (Note 13) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 14) CLK0/CLK0 CLK1/CLK1 Input HIGH Current Input LOW Current CLK CLK 0.5 -150 Min 100 -1 145 -1945 -1 165 -1945 -1525 -1425 Typ 125 -1020 -1820 Max 150 -895 -1600 -880 -1600 -1325 Min 104 -1 145 -1945 -1 165 -1945 -1525 -1425 25C Typ 130 -1020 -1820 Max 156 -895 -1600 -880 -1600 -1325 Min 116 -1 145 -1945 -1 165 -1945 -1525 -1425 85C Typ 145 -1020 -1820 Max 174 -895 -1600 -880 -1600 -1325 Unit mA mV mV mV mV mV
VEE + 1.2 VEE + 0.3
0.0 -0.9 150
VEE + 1.2 VEE + 0.3
0.0 -0.9 150
VEE + 1.2 VEE + 0.3
0.0 -0.9 150
V V mA mA
IIH IIL NOTE:
0.5 -150
0.5 -150
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 11. Input and output parameters vary 1:1 with VCC. 12. All outputs loaded with 50 W to VCC-2.0 V. 13. Single-ended input operation is limited VEE -3.0V in NECL mode. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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NB100LVEP221
HSTL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V
0C Symbol VIH VIL VX IIH IIL NOTE: Characteristic Input HIGH Voltage CLK1/CLK1 Input LOW Voltage CLK1/CLK1 Differential Configuration Cross Point Voltage Input HIGH Current Input LOW Current CLK1 CLK1 -300 680 -150 -150 -250 Vx-100 900 150 -300 680 -150 -150 -250 Vx-100 900 150 -300 680 -150 -150 -250 Vx-100 900 150 mV mV mA mA Vx+100 1600 Vx+100 1600 Vx+100 1600 mV Min Typ Max Min 25C Typ Max Min 85C Typ Max Unit
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
AC CHARACTERISTICS VCC = 0 V; VEE = -2.375 to -3.8 V or VCC = 2.375 to 3.8 V; VEE = 0 V (Note 15)
-40 C Symbol VOpp Characteristic Differential Output Voltage (Figure 3) fout < 50 MHz fout < 0.8 GHz fout < 1.0 GHz Min 550 550 500 Typ 700 700 700 540 590 15 40 1 400 300 49.5 100 800 800 50 200 600 640 50 200 2 1200 1000 50.5 300 400 300 49.5 100 Max Min 600 550 500 25C Typ 700 700 700 540 590 15 40 1 800 800 50 200 660 710 50 200 2 1200 1000 50.5 300 400 300 49.5 150 Max Min 600 500 400 85C Typ 700 700 600 540 590 15 40 1 800 800 50 250 750 800 50 200 2 1200 1000 50.5 350 Max Unit mV mV mV ps ps ps ps ps mV mV % ps
tPLH/tPHL
Propagation Delay (Differential Configuration) CLK0-Qx CLK1-Qx Within-Device Skew (Note 16) Device-to-Device Skew (Note 17) Random Clock Jitter (RMS) (Figure 3) Input Swing (Differential Configuration) (Note 18) (Figure 4) CLK0 CLK1 HSTL Output Duty Cycle Output Rise/Fall Time (20%-80%)
tskew tJITTER VPP
DCO tr/tf
15. Measured with 750 mV source (LVPECL) or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 W to VCC-2 V. 16. Skew is measured between outputs under identical transitions and conditions on any one device. 17. Device-to-Device skew for identical transitions, outputs and VCC levels. 18. VPP is the differential configuration input voltage swing required to maintain AC characteristics. 900 800 700 600 500 400 300 1 200 0.1 0.2 0.4 0.6 0.8 1.0 fIN, INPUT FREQUENCY (GHz) 0 10 9 8 VOPP (mV) 7 6 5 4 3 2 tJITTER ps (RMS)
Figure 3. Output Voltage (VOPP)/Jitter versus Input Frequency (VCC - VEE = 3.3 V @ 255C)
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NB100LVEP221
VCC(LVPECL) VIH(DIFF) VPP VIHCMR VIL(DIFF) VEE VPP VCCO(HSTL) VIH(DIFF) VX VIL(DIFF) VEE
Figure 4. LVPECL Differential Input Levels
Figure 5. HSTL Differential Input Levels
Q Driver Device Q 50 W 50 W
D Receiver Device D
VTT VTT = VCC - 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1405 AND8002 AND8009 AND8020 ECL Clock Distribution Techniques Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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NB100LVEP221
APPLICATIONS INFORMATION Using the thermally enhanced package of the NB100LVEP221 The NB100LVEP221 uses a thermally enhanced 52-lead LQFP package. The package is molded so that a portion of the leadframe is exposed at the surface of the package bottom side. This exposed metal pad will provide the low thermal impedance that supports the power consumption of the NB100LVEP221 high-speed bipolar integrated circuit and will ease the power management task for the system design. In multilayer board designs, a thermal land pattern on the printed circuit board and thermal vias are recommended to maximize both the removal of heat from the package and electrical performance of the NB100LVEP221. The size of the land pattern can be larger, smaller, or even take on a different shape than the exposed pad on the package. However, the solderable area should be at least the same size and shape as the exposed pad on the package. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal conduit. The thermal vias will connect the exposed pad of the package to internal copper planes of the board. The number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. The recommended thermal land design for NB100LVEP221 applications on multi-layer boards comprises a 4 X 4 thermal via array using a 1.2 mm pitch as shown in Figure 7 providing an efficient heat removal path.
All Units mm
supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for the exposed pad package is equivalent to standard surface mount packages. Figure 8, "Recommended solder mask openings", shows a recommended solder mask opening with respect to a 4 X 4 thermal via array. Because a large solder mask opening may result in a poor rework release, the opening should be subdivided as shown in Figure 8. For the nominal package standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should be considered.
All Units mm 0.2 1.0
1.0 4.6 0.2
4.6 Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter Exposed Pad Land Pattern
Figure 8. Recommended Solder Mask Openings
4.6
Proper thermal management is critical for reliable system operation. This is especially true for high-fanout and high output drive capability products. For thermal system analysis and junction temperature calculation, the thermal resistance parameters of the package are provided:
Table 1. Thermal Resistance *
LFPM 0 100 qJA 5C/W 35.6 32.8 30.0 qJC 5C/W 3.2 4.9 6.4
4.6 Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter Exposed Pad Land Pattern
500
Figure 7. Recommended Thermal Land Pattern
The via diameter should be approximately 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via may result in voiding during the solder process and must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will
* Junction to ambient and Junction to board, four-conductor layer test board (2S2P) per JESD 51-8 These recommendations are to be used as a guideline, only. It is therefore recommended that users employ sufficient thermal modeling analysis to assist in applying the general recommendations to their particular application to assure adequate thermal performance. The exposed pad of the NB100LVEP221 package is electrically shorted to the substrate of the integrated circuit and VEE. The thermal land should be electrically connected to VEE.
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NB100LVEP221
PACKAGE DIMENSIONS
LQFP 52 LEAD EXPOSED PAD PACKAGE CASE 848H-01 ISSUE A
M M/2 -Z52 1 4 PL
AJ AJ
40 39
0.20 (0.008) T X-Y Z
PLATING
-XL
-YB AB
AA
J
L/2
13 14 26 27
B/2
D
REF M
0.08 (0.003)
Y T-U
DETAIL AJ-AJ 0.20 (0.008) E X-Y Z
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MM. 3. DATUM PLANE E" IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING PLANE. 4. DATUM X", Y" AND Z" TO BE DETERMINED AT DATUM PLANE DATUM E". 5. DIMENSIONS M AND L TO BE DETERMINED AT BASE SEATING PLANE DATUM T". METAL 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLAND E". 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM D DIMENSION BY MORE THAN 0.08 (0.003). DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE Z FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). DIM A B C D F G H J K L M N P R S V W AA AB AC AD AE MILLIMETERS MIN MAX 10.00 BSC 10.00 BSC 1.30 1.50 0.22 0.40 0.45 0.75 0.65 BSC 1.00 REF 0.09 0.20 0.05 0.20 12.00 BSC 12.00 BSC 0.20 REF 0_ 7_ 0_ --- --- 1.70 12 _ REF 12 _ REF 0.20 0.35 0.07 0.16 0.08 0.20 4.58 4.78 4.58 4.78 INCHES MIN MAX 0.394 BSC 0.394 BSC 0.051 0.059 0.009 0.016 0.018 0.030 0.026 BSC 0.039 BSC 0.004 0.008 0.002 0.008 0.472 BSC 0.472 BSC 0.008 REF 0_ 7_ 0_ --- --- 0.067 12 _ REF 12 _ REF 0.008 0.014 0.003 0.006 0.003 0.008 0.180 0.188 0.180 0.188
A/2 A DETAIL AH -E-TSEATING PLANE
AG
G
48 PL
AG
0.10 (0.004) T
D
52 PL M
0.08 (0.003)
T X-Y
Z
V 0.05 (0.002)
S
AD
EXPOSED PAD 13 14 26 27
S
C
K AE
W N F H DETAIL AH
1 52 40
39
VIEW AG-AG
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CCCC EEEE CCCC EEEE
R
AC
P
0.25
GAGE PLANE
NB100LVEP221
Notes
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NB100LVEP221
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PUBLICATION ORDERING INFORMATION
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NB100LVEP221/D

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